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• Manoj Sinha, "Current Mode Signaling Techniques".
  This web page details an SRC funded project who objective was to develop intuitive current mode signaling techniques that overcome the speed bottlenecks caused by interconnect delay in the deep sub-micron CMOS VLSI circuits.

• Srikanth Arekapudi, Atul Maheshwari, Purushothama Sarva, "High Speed Interconnects for Tile Logic Architecture and Architectural Issues".
  This is a Advanced VLSI Design Project for ECE 659 at Umass. Spring, 2000.

• Advanced 'Nterconnects Synthesis Methods. This is a Advanced VLSI Design Project for ECE 659 at Umass. Spring, 2001.

• Daniel Sumorok, Current Driver With Feedback is an SRC project analyzing the design of a Current Mode driver with feedback and current mode receiver to accomplish multi-bit signaling with reasonable delay.
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