VLSI Circuits and Systems Group
University of Massachusetts Amherst

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Conference Papers

2008 2007 2006 2005 2004 2003 2002 2001 2000 1999 1998
1997 1996 1995 1994 1993 1992

2008

  • J. Jang, O. Franza (Intel), W. Burleson, Period Jitter in Global Clock Trees, IEEE Workshop on Signal Propagation on Interconnects (SPI), 2008.
  • L. Lin, and W. Burleson, Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems, IEEE International Symposium on Circuits and Systems, 2008.
    pdf-link (215kB)
  • V. Arunachalam and W. Burleson, Low-Power Clock Distribution in a Multilayer Core 3D Microprocessor, ACM Great Lakes Symposium on VLSI, 2008.
    pdf-link (561kB)
  • B. Datta and W. Burleson, Collaborative Sensing of On-Chip Wire Temperatures using Interconnect based Ring Oscillators, ACM Great Lakes Symposium on Circuits and Systems, 2008.

2007

  • V. Ambrose, W. Burleson, D. Holcomb, S. Mukherjee, J. Pickholtz, A Fast and Accurate Method for Simulating Soft Errors in Large Combinational Circuits, Intel Design and Test Technology Conf., 2007.
  • D.E. Holcomb, W. Burleson, K. Fu, Initial SRAM state as a fingerprint and source of true random numbers for RFID tags, Proceedings of the Conference on RFID Security, 2007.
    pdf-link (1,013kB)
  • S. Xu, I. Benito, W. Burleson, Thermal Impacts on NoC Interconnects, Poster at the First International Symposium on Networks-on-Chip, 2007.
    pdf-link (200kB)
  • D. Kumar and W. Burleson, Distributed Collaborative Adaptive Sensing: A Unifying Theme for a Junior Level Embedded Systems Course, IEEE Microelectronics Systems Education Conference, 2007.
  • B. Datta, W. Burleson, Low Power and Robust On-Chip Thermal Sensing using Differential Ring Oscillators, International Mid-West Symposium on Circuits and Systems, 2007.
    pdf-link (391kB)
  • B. Datta, W. Burleson, Low Power On-Chip Thermal Sensors based on Wires, International Conference on VLSI-SoC, October 2007.
  • B.Datta, W.Burleson, ThermoWire: A Fast, Robust, low-power Interconnect based thermal sensor, IEEE VLSI-SoC October, 2007.
  • V. Venkatraman and W. Burleson, An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects, IEEE Custom Integrated Circuits Conference (CICC), Sept 2007.
  • R. Vaslin, G. Gogniat, J.-P. Diguet, W. Burleson, and R. Tessier, High-Efficiency Protection Solution for Off-Chip Memory in Embedded Systems, in the Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, June 2007.
  • R. Vaslin, G. Gogniat, J.-P. Diguet, E. Wanderley, R. Tessier and W. Burleson, Low Latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory, in the Proceedings of the International Conference on Reconfigurable Communication-centric SoCs, Montpellier, France, June 2007.

2006

  • I. Benito, V. Venkatraman, W. Burleson, Process Variation-Aware Vdd Assignment Technique for Repeated Interconnects, 49th IEEE International Midwest Symposium on Circuits and Systems, 2006.
    pdf-link (219.3kB)
  • S. Xu, V. Venkatraman and W. Burleson, Energy-Aware Differential Current Sensing for Global On-Chip Interconnects, 49th IEEE International Midwest Symposium on Circuits and Systems, 2006.
    pdf-link (197kB)
  • Tilman Wolf, Shufu Mao, Dhruv Kumar, Basab Datta, Wayne Burleson, and Guy Gogniat. Collaborative monitors for embedded system security, In Proc. of First International Workshop on Embedded Systems Security in conjunction with 6th Annual ACM International Conference on Embedded Software (EMSOFT), Seoul, Korea, October 2006.
  • V. Venkatraman, M. Anders, H. Kaul, W. Burleson, R. Krishnamurthy, A low-swing signaling circuit technique for 65nm on-chip interconnects, IEEE International SOC Conference, Sept. 2006: 289-292.
  • G. Gogniat, T. Wolf, and W. Burleson, Reconfigurable Security Architecture for Embedded Systems, Mobile Computing Hardware Architectures: Design and Implementation Design Symposium (MOCHA 2006), January, 2006.

2005

  • G. Gogniat, T. Wolf, and W. Burleson, Reconfigurable Security Primitive for Embedded Systems, IEEE International Symposium on System-on-Chip (SOC 2005) November, 2005.
  • Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark Anders, Saurabh Dighe, Wayne Burleson, Ram Krishnamurthy, A 2GHz 13.6mW 12x9b Multiplier for Energy Efficient FFT Accelerators, Proc. of the 31st European Solid-State Circuits Conference, Sep. 2005. pdf-file (199.8kB)
  • Vishak Venkatraman and Wayne Burleson, Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations, Sixth International Symposium on Quality of Electronic Design, March 2005, pp: 522-527 pdf-file (131kB)
  • Jinwook Jang, Sheng Xu, Wayne Burleson, Jitter in Deep Sub-micron Interconnect, IEEE Computer Society Annual Symposium on VLSI, 2005. pdf-file (414.4kB)
  • Wayne Burleson and Sheng Xu, Digital Systems Design with ASIC and FPGA: A Novel Course using CD/DVD and On-line Formats, International Conference on Microelectronic Systems Education, 2005. pdf-file (53.6kB)
  • Vishak Venkatraman and Wayne Burleson, Impact of Process Variations on Multi-level Signaling for On-Chip Interconnects, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005.  pdf-file (147.9kB)
  • Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson, Sensing Design Issues in Deep Submicron CMOS SRAMs, IEEE Computer Society Annual Symposium on VLSI, 2005.  pdf-file (44.6kB)
  • N. Salzmann, W. Burleson, K. Rubin, K. Kloesel, S. Cruz-Pol, O. El-Hakim, Challenges in a Multidisciplinary K12 Summer Content Insitute, ASEE 2005.
  • B. Wallace, W. Richards Adrion, W. Burleson, W. Cooper, J. Cori and K. Watts, Using Multimedia to Support Research, Education and Outreach in an NSF Engineering Research Center, Frontiers in Education (FIE), 2005.
  • G. Gogniat, L. Bossuet, and W. Burleson, Configurable computing for high-security/high-performance ambient systems, Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS V) July, 2005.
  • W. Burleson, T. Wolf, R. Tessier, W. Gong, G. Gogniat, Embedded System Security: A Configurable Approach, International Conference on Homeland Security, 2005.
  • O. Hoffman, T. Djaferis, P. Dobosh, W. Burleson, Moving towards a more Systems Approach in a Robotics based Introductory Engineering Course at Mt. Holyoke College, ASEE 2005.
  • C89) N. Salzmann, W. Burleson, K. Rubin, K. Kloesel, S. Cruz-Pol, O. El-Hakim, Challenges in a Multidisciplinary K12 Summer Content Insitute, ASEE 2005.

2004

  • Vishak Venkatraman, Atul Maheshwari , Wayne Burleson, Mitigating Static-Power in Current-Sensed Interconnects, ACM Great Lakes Symposium on VLSI 2004. pdf-file (260kB).
  • Matthew W. Heath, Wayne P. Burleson and Ian G. Harris, Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC’s, Proceedings of Design, Automation and Test in Europe (DATE), Vol. 1, Feb. 2004, pp. 410 - 415 pdf-file(174kB)
  • Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Zhi Zhu, Hempraveen Kukkamalla, Wayne Burleson, NoCIC: A Spice-based Interconnect Planning Tool Emphasizing Aggressive On-Chip Interconnect Circuit Methods, 6th International workshop on System Level Interconnect Prediction, 2004 pdf-file (260kB), ppt-file (2.24MB).
  • M. Heath, W. Burleson and I. Harris, A Deterministic Globally Asynchronous Locally Synchronous (GALS) Methodology for Validation, Debug, and Test, Design Automation and Test in Europe, 2004
  • L. Bossuet, G. Gogniat, W. Burleson, Dynamically Configurable Security for SRAM FPGA Bitstreams, Reconfigurable Architectures Workshop, 2004
  • A. Maheshwari, I. Koren, W. Burleson , Accurate Estimation of Soft Error Rates (SER) in VLSI Circuits, IEEE Conference on Defect and Fault-tolerance in VLSI, 2004

2003

  • Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson Ram Krishnamurthy, Shekhar Borkar, High-Performance and Low Voltage Sense-Amplifier Techniques for Sub-90nm Caches, IEEE ASIC SOC Conference, 2003 pdf-file (202kB).
  • Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne Burleson Ram Krishnamurthy, Shekhar Borkar, Low Voltage Sensing Techniques and Secondary Design Issues for Sub-90nm Caches, European Solid State Circuits Conference, 2003 pdf-file (190kB).
  • Atul Maheshwari and Wayne Burleson, Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects, ACM Great Lakes Symposium on VLSI, 2003 ps-file (276 kB) , pdf-file (100kB).
  • Aiyappan Natarajan, David Jasinski, Wayne Burleson and Russell Tessier, A Hybrid Adiabatic Content Addressable Memory for Ultra Low-power Applications, ACM Great Lakes Symposium Symposium on VLSI, 2003, ps-file (204kB) , pdf-file (88kB).
  • Srividya Srinivasaraghavan and Wayne Burleson, Interconnect Effort - A Unification of Repeater Insertion and Logical Effort, IEEE International Symposium on VLSI, 2003; ps-file (708 kB) , pdf-file (220 kB).
  • J. Chittamuru, and W. Burleson, Dynamic Wordlength Variation for Low-Power 3D Graphics Texture Mapping, IEEE Workshop on Signal Processing Systems, 2003
  • A. Laffely and W. Burleson, Using System on a Chip for VLSI Education, IEEE Microelectronic Systems Education Conference, June 2003
  • A. Laffely, J. Liang, W. Burleson, R. Tessier, Adaptive System on a Chip: A Backbone for Power-Aware Signal Processing Cores, IEEE International Conference on Image Processing, September 2003
  • A. Natarajan, D. Jasinski, W. Burleson, R. Tessier, A Hybrid Adiabatic Content Addressable Memory for Ultra-Low Power Applications, ACM Great Lakes Symposium on VLSI, 2003
  • A. Maheshwari and W. Burleson, Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects , ACM Great Lakes Symposium on VLSI, 2003

2002

  • Atul Maheshwari, Srividya Srinivasaraghavan and Wayne Burleson, Quantifying the Impact of Current-Sensing on Interconnect Delays Trends, IEEE ASIC SOC Conference, 2002  ps-file (352 kB) , pdf-file (128 kB).
  • A. Maheshwari, W. Burleson, R. Tessier, Trading Off Power and Reliability in Ultra-Low Power Systems, IEEE International Symposium on Quality in Electronic Design, March 2002
  • S. Swaminathan, R. Tessier, D. Goeckel, W. Burleson, An Adaptive Viterbi Decoder in FPGAs, FPGA Conference, 2002
  • J. Chittamuru, J. Euh, and W. Burleson, An Adaptive Low Power Texture Mapping Architecture, IEEE Mid-West Symposium On Circuits and Systems, 2002 pp. 204-208
  • J. Euh, J. Chittamuru, and W. Burleson, CORDIC Vector Interpolator for Power-Aware 3D Computer Graphics, IEEE Workshop on Signal Processing Systems, 2002 pp. 426-431
  • W. Burleson, S. Kelley, S. Thampuran, A New Course in Multimedia Systems for Non-Technical Majors, ASEE Engineering Education Conference and Exposition, June 2002, pp. 2793-2802
  • W. Burleson, W. Cooper, J. Kurose, S. Thampuran, K. Watts, An Empirical Study of Student Interaction with CD-based Multimedia Courseware, ASEE Engineering Education Conference and Exposition, June 2002. pp 1430-1443
  • W. Burleson, S. Thampuran N. Ramaswamy, Multimedia Systems: Enabling Computer Engineering Education, IEEE Frontiers in Education Conference, 2002

2001

  • W. Burleson, P. Jain, S. Venkatraman, Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT, IEEE Workshop on Digital and Computational Video, 2001
  • W. Burleson, R. Tessier, D. Goeckel, P. Jain, A. Laffely, Dynamically Parameterized Algorithms and Architectures for Low-Power Signal Processing, International Conference on Acoustics Speech and Signal Processing, 2001
  • Manoj Sinha and Wayne Burleson, Current-Sensing for Crossbars, IEEE ASIC SOC Conference, 2001 ps-file (332 kB) , pdf-file (164kB).
  • Ankireddy Namalpu and Wayne Burleson, A Practical Approach to DSM Repeater Insertion: Satifying Delay Constraints while Minimizing Area and Power, IEEE ASIC SOC Conference, 2001 ps-file (220 kB) , pdf-file (124kB).
  • Ankireddy Namalpu and Wayne Burleson, BOOSTERS: An Alternative to Repeaters for Driving Long On-Chip Interconnects, IEEE International Symposium on Physical Design, 2001 ps-file (2.704 MB), pdf-file (176 kB).
  • Atul Maheshwari and Wayne Burleson, Current-sensing for Global Interconnects, Secondary Design Issues: Analysis and Solutions, IEEE International Workshop on power and timing modeling, optimization and simulation, 2001 ps-file (260 kB) , pdf-file (160 kB)
  • Atul Maheshwari and Wayne Burleson, Current Sensing Techniques for Global Interconnects in Very Deep Submicron (VDSM) CMOS, IEEE Computer Society Workshop on VLSI, 2001. ps-file (220 kB) , pdf-file (136 kB)
  • Ankireddy Nalamalpu and Wayne Burleson, Repeater Insertion in deep sub-micron CMOS: Ramp-based Analytical Model and Placement Sensitivity Analysis, IEEE International Symposium on Circuits and Systems, 2000, ps-file (152 kB), pdf-file (124 kB)
  • S. Thampuran, K. Watts, W. Burleson, CD-MANIC: Multimedia Distance Education without the Wait, IEEE Frontiers in Education, 2001
  • A. Laffely, W. Burleson, R. Tessier, J. Liang, Adaptive System on a Chip for Low-Power Signal Processing, Asilomar Conference on Signal and Systems, October 2001

2000

  • J. Euh, W. Burleson, Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. Workshop on Power-Aware Computing, Fall 2000.
  • J. Peden, W. Burleson, C. Leonardo, The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning, International Conference on Multimedia and Exposition, Aug, 2000.
  • A. Nalamalpu and W. Burleson, Repeater Design in DSM CMOS: Novel Analytical Model and Placement Sensitivity Analysis, International Symposium on Circuits and Systems, 2000.
  • W. Burleson, J. Peden, C. Leonardo, Distributed VLSI Design with the Multimedia Online Collaboration Architecture, European Workshop on Microelectronics Education, May 2000.
  • R. Adrion, J. Kurose, W. Burleson, et al , Multimedia Asynchronous Networked Information Courseware, UMass Instructional Technology Conference, 2000.
  • J. Peden, C. Leonardo, W. Burleson, The Multimedia Online Collaboration Architecture, UMass Instructional Technology Conference, 2000.
  • A. Garcia, W. Burleson, J. Danger, Low Power Digital Design in FPGAs: A Study of Pipeline Architectures Implemented in a FPGA Using a Low Supply Voltage to Reduce Power Consumption, FPGA Conference, 2000. Updated version presented at ISCAS, 2000.

1999

  • W. Burleson, A. Ganz, I. Harris, Educational Innovations in Multimedia Systems, Frontiers in Education Conference, 1999. (Winner of Ben Dasher Award for Best Paper at entire conference.)
  • A. Garcia, W. Burleson, J.L. Danger, Power Modelling in FPGAs, International Conference on Field Programmable Logic and Applications, 1999.
  • W. Burleson, A. Ganz, I. Harris, Multimedia Systems: An Integrated Modular Curriculum, University of Massachusetts Instructional Technology Conference 1999.
  • S. R. Park and W. Burleson, Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures, FPGA Conference, 1999.

1998

  • A. Garcia, W. Burleson, J.L. Danger, Modele de la consommation de puissancedes FPGA, Journees D'Etude Faible Tension, Faible Consommation, Paris, France. 1998, (in French).
  • A. Garcia, W. Burleson, J.L. Danger, Etude sur la consommation de puissance d'un dicodeur MPEG2 ` base des FPGA, Journees D'Etude Faible Tension, Faible Consommation, Paris, France. 1998, (in French).
  • S. R. Park, W. Burleson, Frame-Rate Hardware Reconfiguration for Power Saving in Real-time Motion Estimation, International Conference on Acoustics, Speech and Signal Processing, 1998.

1997

  • A. Brahmbhatt, W. Burleson, FPGA-based Co-processors for Wireless Data Communications, Massachusetts Telecommunications Conference, 1997.
  • M. Petronino, W. Burleson, J. Carswell, J. Mead, R. Bambha, FPGA-based Data Acquisition for 95Ghz Polarimetic Radar, International Conference on Acoustics, Speech and Signal Processing, 1997.
  • W. Burleson and M. Ciesielski, Using Computers to Design Computers: Novel Instructional Technology in Computer Systems Engineering, UMASS Instructional Technology Conference, 1997.

1996

  • B. Jung and W. Burleson, VLSI Array Architectures for Pyramid Vector Quantization, VLSI Signal Processing Workshop 1996.
  • W. Burleson, Integrating Manufacturing into a Computer Systems Design Course: Design Technology and Industrial Collaboration, IEEE Frontiers in Education Conference, 1996.
  • M. Stan, and W. Burleson, Two-dimensional Codes for Low-Power, International Symposium on on Low-Power Electronics and Design, 1996.
  • M. Stan, Wayne P. Burleson, Synchronous Up/Down Counter with Period Independent of Counter Size, FPGA Conference, 1996.

1995

  • M. Stan, and W. Burleson, Low-Power CMOS Clock Drivers, ACM Workshop on Timing in Digital Systems, 1995.
  • T. Kim, W. Burleson and M. Ciesielski, Constrained Timing Synthesis and Delay insertion with Application to Wave-pipelining, ACM Workshop on Timing in Digital Systems, 1995.
  • R. Grupen, C. Connolly, K. Souccar, and W. Burleson, Toward a Path Co-Processor for Automated Vehicle Control, IEEE Symposium on Intelligent Vehicles, 1995.
  • Z. Zhou , W. Burleson, Equivalence Checking of Datapaths based on Canonical Arithmetic Expressions, Design Automation Conference, San Francisco, 1995.
  • M. Stan and W. Burleson, Coding a terminated bus for Low-power, Great Lakes Symposium on VLSI, 1995.
  • Y. Jeong, W. Burleson, High-level Estimation of High-Performance Architectures for Reed-Solomon Decoding, International Symposium on Circuits and Systems, 1995. pp. I-720-723.
  • B. Jung, W. Burleson, Real-Time VLSI Compression for Wireless Local Area Networks, Data Compression Conference, 1995. p 431.

1994

  • W. Burleson, M. Ciesielski, W. Cotten and F. Klass, Is Wavepipelining Practical?, (A forum session), Proceedings of International Symposium on Circuits and Systems, 1994.
  • H. Choi and W. Burleson, Search-based Wordlength Optimization in VLSI/DSP Synthesis, VLSI Signal Processing Workshop, 1994.
  • W. Burleson, C. Lee and E. Tan, A 150 Mhz Wave-pipelined Adaptive Digital Filter in 2 micron CMOS, VLSI Signal Processing Workshop, 1994.
  • B. Jung, Y. Jeong and W. Burleson, Distributed Control Synthesis for Data-Dependent Iterative Algorithms, Conference on Application-Specific Array Processors, 1994.
  • M. Stan and W. Burleson Limited-weight codes for low-power I/O, International Workshop on Low-Power Design, 1994.
  • B. Jung and W. Burleson, A VLSI Systolic Array Architecture for Lempel-Ziv-based Data Compression", International Symposium on Circuits and Systems, 1994.
  • W. Burleson, Using Regular Array Methods for DSP Module Synthesis, Hawaii International Conference on System Sciences, 1994, p. I-58-67 (an invited session).

1993

  • T. S. Kim, W. Burleson, and M. Ciesielski,Delay buffer insertion for Wave-pipelined Circuits, International IFIP Workshop on Logic and Architecture Synthesis, France 1993.
  • D. Niehaus, K. Ramamritham, J. Stankovic, G. Wallace, C. Weems, W. Burleson, J. Ko, The Spring Scheduling Coprocessor: Design, Use and Performance, Proceedings of the Real Time Systems Symposium, 1993.
  • W. Marvin, W. Burleson, D.S. Phatak, Full Simulation of Optical Neural Nets, Proc. of SPIE Conference on Neural Networks, 1993.
  • H. Choi, W. Burleson, D.S. Phatak, Fixed-Point Roundoff Error Analysis of Large Feedforward Neural Nets, International Joint Conference on Neural Networks, 1993.
  • Z. Zhou, W. Burleson, Formal Descriptions, Semantics and Verification of VLSI Array Processors, International Conference on Application-Specific Array Processors, 1993, pp. 321-332.
  • B. Jung, W. Burleson, Node-Merging: A Transformation on Bit-level Dependency Graphs, International Conference on Application-Specific Array Processors, 1993, p. 442-453.
  • Y. Jeong, W. Burleson, VLSI Array Synthesis for Polynomial GCD Computation, International Conference on Application-Specific Array Processors, 1993, p. 536-547, (1 of 19 full-length papers accepted out of 121 submitted).
  • H. Choi, W. Burleson, D.S. Phatak, Optimal Wordlength Assignment for the Discrete Wavelet Transform in VLSI, Workshop on VLSI Signal Processing, 1993, p. 325-333.
  • W. Burleson, J. Ko, D. Niehaus, K. Ramamritham, J. Stankovic, G. Wallace, C. Weems, The Spring Scheduling Coprocessor: A Scheduling Accelerator, International Conference on Computer Design, 1993, p. 140-144.
  • T. S. Kim, W. Burleson, M. Ciesielski, Logic Restructuring for Wave-pipelining, International Workshop on Logic Synthesis, 1993.
  • J. D. Narkiewicz, W. Burleson, Rank-Order Filtering Algorithms: A Comparison of VLSI Implementations, International Symposium on Circuits and Systems, 1993.
  • J. D. Narkiewicz, W. Burleson, VLSI Performance/Precision Tradeoffs of Approximate Rank-Order Filters, Workshop on VLSI Signal Processing, p. 185-194.

1992

  • M. Stan, W. Burleson, Analog VLSI for Robot Path Planning, Asilomar Conference on Signals, Systems and Computers, 1992, p. 915-919.
  • W. Burleson, B. Jung, ARREST: An Interactive Graphic Design Tool for VLSI Arrays, International Conference on Application Specific Array Processors, 1992, p. 149-162.
  • Y.Jeong, W. Burleson, Choosing VLSI Algorithms for Finite Field Arithmetic, International Symposium on Circuit and Systems, 1992, p. 799-802.
  • W.-H. Lien, W. Burleson, Wave-Domino Logic: Theory and Application, International Symposium on Circuit and Systems, 1992, p. 2949-2952. (also presented at ACM/SIGDA Workshop on Timing Issues in the Specification of Digital Systems, 1992)