Synopsys^TM

Synopsys for Standard Cell Layout

Use /cse2/synopsys/doc/online/top.pdf for official help

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Outline of design procedure: This page outlines the synopsys design procedure for generating a netlist compatible with the Virginia Tech VLSI for Telecommunications standard cell library. The verilog file for a 16 bit carry look ahead adder, cla.v is used as an example. If you have the vlsix directory you will find all the files you need in that hierarchy. Start by testing the adder in verilog with the following stimulus modulecla_stim.v and configuration modulecla.cfg. I suggest creating a new design directory as the following process creates a large number of files. For this example I have created the directory vlsix/verilog/adder16 and will run everything from there.

0. There are several important files you will need to access.

/mnt1/cadence/cadence/ncsu/local/lib/Synopsys_Libraries/

- directory for Synopsys standard cell library

/mnt1/cadence/cadence/ncsu/local/lib/Synopsys_Libraries/vtvtlib25.db

- The actual library

All these steps can be somewhat automated in dc_shell using the example script.
1. In your design directory type:

example> design_analyzer

2. The Synopsys Design Analyzer will come up now click on Setup>Defaults and enter the following data:

Designer: "your name"
Company: UMASS
Search Path: /mnt1/cadence/cadence/ncsu/local/lib/Synopsys_Libraries
Link Library: vtvtlib25.db
Target Library: vtvtlib25.db
Symbol Library: vtvtlib25.db
Schematic Options: -size infinite

Click OK. You can set these in the file .synopsys_dc.setup and never have to type them again.

3. Click File -> Read and use the window to select your design.

4. VHDL only (Skip if your design is in verilog) Click File -> Analyze and select your design. You may use the default WORK directory as the Library.

5. VHDL only (Skip if your design is in verilog) Click File -> Elaborate and select the Library you previously used, i.e. "WORK". You may have to Scroll to find it. Your design will be in this temporary location and will now be all in CAPITAL LETTERS with the caption (BEHAVIOR). Select your design and OK.

6. Now in the Synopsys Design Analyzer window select your design by clicking on it once. You can look at the hierarchy by double clicking on it or using the up and down arrows to the left. When your design is selected it will have dashed lines as opposed to the normal solid.

7. If you call submodules more than once you will need to select the top module and click Edit -> Uniquify -> Hierarchy. This will place all the instances in the Design Analyzer Window.

8. Select the top module and click Tools>Design Optimization and Map Design and Verify Design. If it is a large design run it in the Background. If so you will have to click OK in another window to start the process.

9. Select the top module click File -> Save As. Change the file name to "your_design".v and select verilog as the output format. This is your netlist of standard cell you will need in the Cadence tools.

10. Go to Silicon Ensemble to make a layout.