System Design:

Given: NOR Gate

Back to Logic Design:

Back to Circuit Design:

Layout Design:

The circuit design stage shows you to run the automatic layout generation procedure. The automatic layout generated is not a very optimal layout in terms of area. Nor does it fit in thelibrary specifications that we want. So the next step is to design the layout manually. This is also the last step of the design.

Use the layout editor to design a CMOS layout of your 2-input NAND gate. Attempt to minimize the width of the gate. Open the layout editor window in Microwind (Microwind2). Click on File -> Select Foundry and select cmos025.rul. this sets your layout editor designs in 0.25u technology.

  The problem specifications are 100 lambda height and 20 lambda hieght for Vdd and GND rails. So we will place Vdd and GND rails of 20 lambda height and spaced 60 lambda apart. Vdd and GND rails are in Metal1. The top rail is used as Vdd and the bottom one as GND. To create a metal rectangle click on Metal 1 in the palette and then create the required rectangle in the layout window.

The next step is to build the NMOS transistors. These are in parallel for a NOR gate. Click on the transistor symbol in the palette. A Layout Generator Window appears. Click on MOS in it. Set the W, L of the transistor. Set the type (nmos/pmos). Check the units of the sizes (lambda/micron).

Then click on Generate device and place it in the layout. The source of the transistor is connected to the GND rail. Create another device in a similar manner to place it in parallel to the first NMOS device. We share the two devices' drain diffusions. This saves on area as well as reduces capcitances. At any stage of designing the layout, you can run a DRC check to see if your design has any errors. A DRC check can be run by clicking on Analysis -> Design Rule Checker.

The next step is to place two PMOS transistors in series.

Place the PMOs transistor on the layout close to the Vdd rail on the top. To construct two PMOS transistors in series, the diffusions are shifted to a side and another poly line is added as the second transistor. Once again, the diffusion is shared to save area and reduce capcitance. In the figure below, the p diffusion in the pmos transistor was stretched to the left and a second poly line was added. To add a poly line click on polysilicon in the palette and create the required size rectangle in the layout window.

The next step is to connect the inputs (poly) and the output of the two transistors.

Poly inputs are connected

Metal output is connected.

The next step is to connect the poly to metal1 and then to metal2. The first symbol in the first row of the palette is the poly to metal1 contact. Select this to contact poly to metal 1 as shown in the figure.

Then we connect the metal1 to metal2 contact to the previous contact. This is the 4th contact on the first row.

The next step is to connect the output Metal1 to Metal2. Once again use the 4th contact in the first row.

Now we connect metal2 to the two inputs and one output and bring them to the top to go out of the cell. Observe the tow inputs (left & right) and an output (middle) above the Vdd rail in dark blue color.

Now we label the inputs and output as In1, In2 and out. Click on Add a Pulse Symbol in the palette (5th from the right in the 3rd row). Then click on the metal2 of one of the inputs. A window appears as shown in the figure below. Change the name of the input signal. Insert a 01 sequences and click on Insert. The click on Assign. Similarly assign the 2nd input a pulse.

Now select the Visible Node symbol from the palette (7th in the third row). Select it and click on the output. The 'Add a Visible Property' window appears. Change the label name to out. Slect Visible in Simulation. Click on Assign. Now the output is also labeled.

Now assign labels to the Vdd and GND nodes. Select Vdd Supply and GND from the palette (third row). Click on the rails to assign it Vdd or GND. Also click on the capacitor (3rd in 2nd row) symbol and add it to the output. Give it the value calculated in the hand calculations at the output.

Also, extend the pwell into the Vdd Rail. The click on Edit -> Generate -> Contacts. A window appears as shown. Select PATH and then in Metal choose Metal1 and N+ polarization. The Click on start path and make contacts on the Vdd rail as shown below.

At this point your layout is ready to be posted.

Verify the functionality of the layout.

To run the Simulation of your circuit, click on Simulate -> Start Simulation. Depending on the input sequences assigned at the input the output is observed in the simulation. The power value is also given. Make tphl, tplh and tp measurements, by changing the input sequences and clicking and dragging the mouse on the waveform in the horizontal direction. Most of the times, Microwind automatically provides with the rise and fall delays on the waveforms. The power consumption is also available at the bottom right of the window.