System Design:

Given: NOR Gate

Back to Logic Design:

Circuit Design:

Calculate the required transistor sizes by hand. Justify your assumptions.

Simulate your system with your hand calculated transistor sizes.

Open the schematic you created in the logic design stage. The next step is to convert this schematic into a Verilog representation.

Click on File -> Make Verilog File. The Verilog, Hierarchy and Netlist window appears. This window shows the verilog representation of your (Nor gate in this example) circuit. Click on OK. This saves the Verilog file as a .txt file in your present directory. Your circuit is now saved as a Verilog file. Close the schematic editor window.

Open the layout editor window in Microwind (Microwind2). Click on File -> Select Foundry and select cmos025.rul. this sets your layout editor designs in 0.25u technology.

Click on Compile -> Compile Verilog File. An Open Window appears. Select the .txt verilog file saved before and open it.

After selecting the .txt file, a new window appears called Verilog file.

f. Click on Size on the right top menus. This shows up the NMOS and PMOS sizes. Set the sizes according to your hand calculations.

Then Click on Compile and then Back to editor in the Verilog File Window. This creates a layout in your layout editor window. You have now gone through an automatic layout generation procedure in Microwind.

Also add a capacitance to the output of the design you have made. The capacitance is available in the Palette as the third symbol in the 2nd row. The value of the capacitance should be what was calculates in your hand calculations.

Click on OK. The capacitance is shown on the left bottom corner with a value of 0.015fF.

Click on the label marked In1. A window appears. Click on the Pulse option in the window. Insert a 01 sequence for that specific input and click on Insert. Then click on Assign. Perform this assignment on the other inputs also.

Click on Simulate -> Run simulation. A simulation window appears with the inputs and output being shown. Measure the tphl, tplh and tp of the circuit using this simulation window. You can click and drag in the simulation window in the horizontal direction to make a measurement. Rising and falling delays are also shown on the output waveform. The power consumption is also shown on the right bottom portion of the window.

If you are unable to meet the specifications of the circuit as given in the lab description, change the sizes as shown in f. Generate the layout again and run the simulations till you achieve your target delays.
 

Next Step : Layout Design