Design Flow

U-Mass supports 2 types of custom IC design:

Full Custom: The designer creates layout masks by hand.

Standard Cell: (Thanks to NCSU and VTVT) The designer uses verilog code to describe the system and lets the computer make the masks.

The full custom flow can produce very compact layouts, which run fast, but doing so can be involved. Using standard cells greatly reduces designer workload, but the resulting implementations can have wasted area and typically run slower. The following design flow and links are intended to introduce you to the tools involved. Each link contains an example of the approach or a tool you may use.

Full Custom: There is a nor and example in the vlsix58.tar.gz file with all the steps complete.

Architecture Design: The first step is the architecture design. VerilogXL allows you to specify and test your system at the behavioral level.

Logic Design: Using the Cadence schematic editor in icms, you can develop and extract a schematic of your system. Logic verification can be done with either VerilogXL or IRSIM, a simple logic simulator. Both require modifications to the extracted netlist, but these perl scripts should do it nicely. (schm2vlog.pl for Verilog) or (schm2sim.pl for IRSIM). The Cadence tool icms also has a the to simulate a design using Verilog. I have found this to be cumbersome, but you may attempt this by reviewing the process in cdsdoc (AMS tools).

Circuit Design This differs from logic design in that you must now account for the electrical properties of the devices. The first step is to calculate the approximate size of the transistors by hand calculations. After this, modify the properties of the transistors in your schematic to match your calculations. Verify both the speed and power consumption of your design using either extracted netlists and hspice or Spectre inside icms. (schm2spice.pl will help modify the extracted netlist for hspice)

Layout Design: After your schematic is verified and simulated you will actually build the mask layers in the layout editor. Now you must perform 2 steps to assure your layout works properly.

- First you should verify the logic. You can do this using the layout vs. schematic option in layoutPlus or by extracting the circuit and running either Verilog (via lo2vlog.pl) or IRSIM (via lo2sim.pl).
- After verifying the functionality, you should re-simulate the system for performance using hspice (via lo2spice.pl).

Standard Cell Design:

Architecture Design: The first step is the architecture design. VerilogXL allows you to specify and test your system at the behavioral level.

Layout Synthesis: You will use 2 tools:

- Synopsys will link your verilog code to the standard cell library. The result is a netlist of standard cells.
- Silicon Ensemble takes the netlist and places and routes the cells.

Layout Verification and Simulation: After the layout is generated you can use the tools to verify and simulate your system.

- First you should verify the logic. You can do this by extracting the circuit and running either Verilog (via lo2vlog.pl) or IRSIM (via lo2sim.pl).
- After verifying the functionality, you should extract with parasitics and simulate the system for performance using hspice (via lo2spice.pl).